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ESDALC6V1-1M2
Single line low capacitance TransilTM for ESD protection
Features

Single line low capacitance Transil diode Unidirectional ESD protection ESD protection > 30 kV (IEC 61000-4-2 contact discharge) Breakdown voltage VBR = 6.1 V min. Low diode capacitance (22 pF @ 0 V) Low leakage current (< 100 nA @ 3 V) Very small PCB area (0.6 mm2) RoHS compliant Figure 1. Functional diagram
SOD882 Package
Benefits

High ESD protection level High integration Suitable for high density boards
I/O1
Complies with the following standards:
IEC 61000-4-2 level 4 - 15 kV (air discharge) - 8 kV (contact discharge) MIL STD 883G - Method 3015-7: class 3B - HBM (Human body model)
GND I/O2 3
GND
Applications
Where transient overvoltage protection in ESD sensitive equipment is required, such as:

Description
The ESDALC6V1-1M2 is a unidirectional single line TVS diode designed to protect the data lines or other I/O ports against ESD transients. The device is ideal for applications where both reduced line capacitance and board space saving are required.
Computers Printers Communication systems Cellular phone handsets and accessories Video equipment
TM: Transil is a trademark of STMicroelectronics
November 2007
Rev 5
1/10
www.st.com
Characteristics
ESDALC6V1-1M2
1
Table 1.
Symbol VPP PPP IPP Tj Tstg TL TOP
Characteristics
Absolute maximum ratings (Tamb = 25 C)
Parameter ESD discharge - IEC 61000-4-2 contact discharge Peak pulse power dissipation (8/20 s) (1) Repetitive peak pulse current (8/20 s) Junction temperature Storage temperature Maximum lead temperature for soldering during 10 s at 5 mm for case Operating temperature range Tj initial = Tamb Value 30 50 6 125 - 55 to +150 260 - 40 to + 125 Unit kV W A C C C C
1. For a surge greater than the maximum values, the diode will fail in short-circuit
Table 2.
Symbol VRM VBR VCL IRM IPP T VF
Electrical characteristics
Parameter Stand-of voltage Breakdown voltage Clamping voltage Leakage current @ VRM Peak pulse current Voltage temperature coefficient Forward voltage drop VBR @ IR IRM @ VRM nA max 100 V 3 RD typ 0.5 VF @ 10 mA V max 1 T 10-4/C max 4.5 C@0V pF typ 22
Slope= 1/ Rd I PP VCL VBR VRM I RM IR VF V I
IF
Order code Vmin Vmax mA ESDALC6V1-1M2 6.1 7.2 1
Figure 2.
Peak power dissipation versus initial junction temperature
Figure 3.
PPP(W)
Peak pulse power versus exponential pulse duration
PPP[T j initial] / PPP [T j initial=25C] 1.1 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 0 25 50 75 100 125 150
1000
100
T j(C)
tP(s)
10 1 10 100
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ESDALC6V1-1M2
Characteristics
Figure 4.
Clamping voltage versus peak pulse current, rectangular waveform
Figure 5.
Forward voltage drop versus peak forward current (typical values)
100.0
IPP(A)
1.E+00
8/20 s Tj initial =25 C
IFM(A)
Tj =25 C
1.E-01
10.0
Tj =125 C Tj =-40 C
1.E-02
1.0
1.E-03
VCL(V)
0.1 0 5 10 15 20 25 30 35 40
1.E-04 0.2 0.4 0.6 0.8 1.0
VFM(V) 1.2 1.4
Figure 6.
Capacitance versus reverse applied Figure 7. voltage (typical values)
Relative variation of the leakage current versus junction temperature (typical values)
C(pF)
25
F=1 MHz VOSC=30 mVRMS Tj=25 C
IR [T j] / IR [T j=25C]
100
VR =3V
20
15
10
10
5
VR(V)
0 0 1 2 3 4 5
1 25 50 75 100
T j(C)
125 150
Figure 8.
ESD response to IEC 61000-4-2 (+15 kV air discharge) on each channel
Figure 9.
ESD response to IEC 61000-4-2 (-15 kV air discharge) on each channel
21V
- 15V
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Ordering information scheme
ESDALC6V1-1M2
Figure 10. S21 attenuation measurement result
Attenuation APLAC 7.91 User: ST Microelectronics Apr 04 2006 0.00
- 3 dB
270 MHz
-10.00
-20.00
-30.00
1.81 GHz
-40.00 100.0k 1.0M ESDALC6V1-1M2 10.0M f/Hz 100.0M 1.0G
2
Ordering information scheme
Figure 11. Ordering information scheme
ESDA LC 6V1 - 1M2
ESD Array Low Capacitance Breakdown Voltage 6V1 = 6.1 Volts min Package M2 = SOD882
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ESDALC6V1-1M2
Package information
3
Package information
Epoxy meets UL94, V0
In order to meet environmental requirements, ST (also) offers these devices in ECOPACK(R) packages. ECOPACK(R) packages are Lead-free. The category of second level Interconnect is marked on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com. Table 3. SOD882 dimensions
Dimensions
D
INDEX AREA (D/2 xE/2)
Ref
E
Millimetres Min Typ 0.47 Max Min
Inches Typ Max
A
TOP VIEW
0.40 0.00 0.20 0.20
0.50 0.016 0.019 0.020 0.05 0.000 0.002
A1
A1
b1 b2 D
0.25 0.25 1.00 0.60 0.65
0.30 0.008 0.010 0.012 0.30 0.008 0.010 0.012 0.039 0.024 0.026 0.55 0.018 0.020 0.022 0.55 0.018 0.020 0.022
A
SIDE VIEW
b1
INDEX AREA (D/2 xE/2)
b2
E
L2
L1
e L1 L2 0.45 0.45
OPTIONAL PIN#1 ID e
BOTTOM VIEW
0.50 0.50
Note:
Product marking may be rotated by 90 for assembly plant differentiation. In no case should this product marking be used to orient the component for its placement on a PCB. Only pin 1 mark is to be used for this purpose. Figure 12. Footprint (dimensions in mm) Figure 13. Marking
0.55 0.55
0.50
Pin1
N
Pin 2 Pin 2
0.40
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Package information Figure 14. Tape and reel specifications
Cathode bar
ESDALC6V1-1M2
2.0 0.05 0.20 0.05
4.0 0.1
O 1.55 0.05
1.75 0.1
1.10 0.05
N N
3.5 - 0.05
0.66 0.05 (C-PAK) 0.55 0.1 (3M)
All dimensions in mm
8.0 0.3
0.68 0.05
User direction of unreeling
N
N
N
2.0 0.1
N
N
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ESDALC6V1-1M2
Recommendation on PCB assembly
4
4.1
Recommendation on PCB assembly
Stencil opening design
1. General recommendation on stencil opening design a) Stencil opening dimensions: L (Length), W (Width), T (Thickness).
Figure 15. Stencil opening dimensions
L
T
W
b)
General design rule Stencil thickness (T) = 75 ~ 125 m W Aspect Ratio = ---- 1.5 T LxW Aspect Area = --------------------------- 0.66 2T ( L + W )
2.
Reference design a) b) Stencil opening thickness: 100 m Stencil opening for leads: Opening to footprint ratio - between 60% and 65%.
Figure 16. Recommended stencil windows position
Package footprint
Lead footprint on PCB Lead footprint on PCB
Stencil window position
0.39 mm
Stencil window position
0.45 mm 0.05 mm 0.05 mm
4.2
Solder paste
1. 2. 3. 4. Halide-free flux qualification ROL0 according to ANSI/J-STD-004. "No clean" solder paste is recommended. Offers a high tack force to resist component movement during high speed Solder paste with fine particles: powder particle size is 20-45 m.
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Recommendation on PCB assembly
ESDALC6V1-1M2
4.3
Placement
1. 2. 3. 4. Manual positioning is not recommended. It is recommended to use the lead recognition capabilities of the placement system, not the outline centering Standard tolerance of 0.05 mm is recommended. 3.5 N placement force is recommended. Too much placement force can lead to squeezed out solder paste and cause solder joints to short. Too low placement force can lead to insufficient contact between package and solder paste that could cause open solder joints or badly centered packages. To improve the package placement accuracy, a bottom side optical control should be performed with a high resolution tool. For assembly, a perfect supporting of the PCB (all the more on flexible PCB) is recommended during solder paste printing, pick and place and reflow soldering by using optimized tools.
5. 6.
4.4
PCB design preference
1. 2. To control the solder paste amount, the closed via is recommended instead of open vias. The position of tracks and open vias in the solder area should be well balanced. The symmetrical layout is recommended, in case any tilt phenomena caused by asymmetrical solder paste amount due to the solder flow away.
4.5
Reflow profile
Figure 17. ST ECOPACK(R) recommended soldering reflow profile for PCB mounting
Temperature (C)
260C max 255C 220C 180C 125 C
2C/s recommended 2C/s recommended 6C/s max 6C/s max
3C/s max 3C/s max
0 0 1 2 3 4 5
10-30 sec 90 to 150 sec 90 sec max
6
7
Time (min)
Note:
Minimize air convection currents in the reflow oven to avoid component movement.
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ESDALC6V1-1M2
Ordering information
5
Ordering information
Table 4. Ordering information
Marking N(1) Package SOD882 Weight 0.92 mg Base qty 3000 Delivery mode Tape and reel
Order code ESDALC6V1-1M2
1. The marking can be rotated by 90 to diferentiate assembly location
6
Revision history
Table 5.
Date 23-May-2006 16-Jun-2006 11-Oct-2006 10-May-2007
Document revision history
Revision 1 2 3 4 Initial release Updated tape and reel illustration (Figure 13). Corrected formatting errors on page 1. No technical changes. Updated Functional diagram to single diode. Added Section 4: Recommendation on PCB assembly. Corrected 2: Ordering information scheme. Updated Figure 14: Tape and reel specifications. Added Figure 16: Recommended stencil windows position. Reformatted to current standards. Changes
26-Nov-2007
5
9/10
ESDALC6V1-1M2
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